• Simulator independent: currently out-of-the-box support for Eldo (TM), HSPICE (R), LTSpice (TM), Spectre (R), Qucs and ngspice exist. More are to be included in future releases.
• Number of variables: there is, in theory, no limit to the number of circuit variables that can be optimized, except those constraints imposed by the available computer memory and/or the time required to generate a functional circuit. It is currently hardcoded in the C code.
• PVT corners: by using the simulator functionality, the possibility to test various design corners and Monte Carlo analysis is only limited to the simulator capability and by the time it takes to finish the optimization.
• Efficiency: the optimization algorithm features a global optimization using differential evolution. It has been used on a variety of applications and is known to produce good results in an acceptable time. Furthermore, this algorithm can be chained with a local optimizer to gain convergence speed as suggested by open literature.
• Parallel/distributed computation: time savings are achieved by simultaneously evaluating the proposed values over multiple computers on the network. No limit exists on the total number that can be used concurrently.
• Within the supported SPICE simulators, an arbitrary netlist can be optimized on different conditions without having to recompile the code.
• File format: all outputted data and log information is stored in plain text format. This guarantees that they will always be readable in the future. In addition, it makes possible the use of other existing tools to post-process the optimization results.
• It is free software: the code is available under the GNU GPL license.

ASCO has been designed to address problems that are oriented to electric circuits. Although not limited, some possible applications can include:

• Fully redesign a new circuit described in a SPICE netlist.
• Reuse, optimize an existing circuit.
• Migrate an existing and working design to a more advanced semiconductor technology process effortlessly.
• Increase the robustness and yield of an already designed circuit by guaranteeing that it comply with all design goals and constraints in some/all process corners at will.
• Easily explore a new operating point (design space) of an already existing topology, to reduce power consumption, area or both.
• Look for a feasible new design topology before investing a considerable time trying to derive equations that describe its operation.